Error correction codes (ECC's) have been used to protect data stored in a wide variety of memory systems. Magnetic discs, magnetic tapes, laser optical discs and semiconductor memories have all been protected by various ECC's. Some codes can correct only a single bit and require only a small number of check bits while others can correct many bits but require a much larger number of check bits. Those codes that correct many bits are sometimes referred to as burst ECC's.
In order to more effectively utilize simple, single error correcting codes, various data organizations have been adopted that disperse the data such that a single occurrence of an error does not show up as a burst error, thus exceeding the correction capability of the code. For instance, one application has used a four bit Hamming code plus a parity bit to protect a byte of data. The total data word is then 13 bits wide. The data is spread out via an interleaving technique such that each adjacent bit in the data byte is 14 bits away. This technique involves writing to the rows of a memory matrix and reading from columns.
Another application of this same technique has been used to disperse the bits of a convolution code and achieve burst error correction. The technique has also been applied multiple times in yet another application to disperse the bits of a data byte more than a single interleave allows.
The applications of bit-level interleaving mentioned above apply simple ECC's to relatively error-prone information channels. They attempt to maximize the effectiveness of these simple codes relative to the error characteristics of the channel.
The characteristics of a semiconductor memory, such as a write cache for a disc drive storage array, differ considerably from an ordinary information channel to which the prior art applications have been directed in that the memory is normally relatively error-free, although prone to occasional catastrophic failure due to the loss of a data bus bit or memory device in the memory array that comprises the semiconductor memory. It is desirable that such a memory utilizes a powerful multi-burst error correction code, such as described in U.S. Pat. No. 5,107,503 by Riggle et al., entitled High Bandwidth Reed Solomon Encoding, Decoding and Error Correcting Circuit, which is a continuation of Ser. No. 136,206, filed Dec. 21, 1987, now abandoned, which is a continuation of Ser. No. 88,378, filed Aug. 24, 1987, now abandoned, to provide fault tolerance for such catastrophic bus errors or entire memory device failures. However, in known prior art memories the organization of data that is written is not optimal to maximize resistance to catastrophic memory failure, even with the utilization of the Reed-Solomon ten bit symbol error correction code described above. This is partly due to the fact that a data bus error or memory device failure can cause the loss of more than one ten bit symbol, thus limiting the effectiveness of the error correction code in protecting the integrity of data blocks.
Therefore, it is desirable to re-order or organize the data stored as ten bit symbols in the memory to maximize resistance of stored data blocks to catastrophic data bus errors or memory device failure.